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ds07-12508-3e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l MB89601r series MB89601r/603/p601/pv620 n description the MB89601r series is compact one-chip microcontrollers using the f 2 mc-8l* cpu core for which can operate at low voltage but at high speed. the microcontrollers contain peripheral functions such as timers, a serial interface and an external interrupt and are applicable to welfare products, especially portable devices required savings in board space. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? high-speed processing at low voltage minimum execution time: 0.5 m s/3.5 v at 8 mhz ?f 2 mc-8l family cpu core ?timer 8-bit pwm timer (also usable as a reload timer) ? serial interface switchable transfer direction allows communication with various equipment. ? external interrupt capable of wake-up from low-power consumption modes (with an edge detection function) ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) n pac k ag e 48-pin plastic sqfp (fpt-48p-m05) 64-pin ceramic mdip (mdp-64c-p02) 64-pin ceramic mqfp (mqp-64c-p01)
MB89601r series 2 n product lineup (continued) mb89603 mb89p601 mb89pv620 *1 classification mass production products (mask rom products) one-time prom product piggyback/evaluation product (for evaluation and development) rom size (internal rom) 4 k 8 bits (internal mask rom) 8 k 8 bits (internal mask rom) 4 k 8 bits (external rom, programming with general-purpose eprom programmer) 32 k 8 bits (external rom) ram size 80 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.5 m s/8 mhz interrupt processing time: 4.5 m s/8 mhz por ts input ports: 1 (also serve as peripherals.) output ports: none i/o ports (n-ch open-drain): 8 (3 ports also serve as peripherals) output ports (cmos): none i/o ports (cmos): 24 (1 port also serves as peripherals.) to t a l : 3 3 5 (4 ports also serve as peripherals.) 8 (8 ports also serve as peripherals.) 8 (4 ports also serve as peripherals.) 8 (8 ports also serve as peripherals.) 24 (24 ports also serve as peripherals.) 53 8-bit pwm timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.5 to 8 m s) 8-bit resolution pwm operation (conversion cycle: 128 to 2048 m s) 8-bit pulse-width count timer none 8-bit timer operation 8-bit reload timer operation 8-bit pulse-width measurement operation 16-bit timer/counter none 16-bit timer operation 16-bit event conter 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.0 m s, 4.0 m s, 16.0 m s) si/o 2 channels 8-bit a/d converter none 8-bit resolution 8 channels a/d conversion mode sense mode reference voltage input external interrupt edge selection, interrupt vector, source flag rising edge/falling edge selectability used also for wake-up from stop/sleep modes. (edge detection is also permitted in stop mode.) external interrupt 4 channels MB89601r part number parameter
MB89601r series 3 (continued) *1: the piggyback/evaluation product is applicable to the mb89620 series. *2: varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the MB89601r, mb89603, mb89p601, upper than 0140 h of each register bank cannot be used. ? the stack area, etc., is set at the upper limit of the ram. ? external area is used. 2. current consumption ? in the case of the mb89pv620, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check n mask options. take particular care on the following point: ? options are fixed on the mb89pv620 and mb89p601. mb89603 mb89p601 mb89pv620 *1 standby mode sleep mode, stop mode process cmos operating voltage *1 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c256a-20tv mbm27c256a-20cz package MB89601r mb89603 mb89p601 mb89pv620 dip-48p-m05 mdp-64c-p02 mqp-64c-p01 MB89601r part number parameter
MB89601r series 4 n pin assignment 13 14 15 16 17 18 19 20 21 22 23 24 n.c. rst p60/int p30 p31 p32 p33 p34 p35 p36 p37/pto n.c. 36 35 34 33 32 31 30 29 28 27 26 25 n.c. mod1 p07 p06 p05 p04 p03 p02 p01 p00 v cc n.c. n.c. x1 x0 p40 p41 p42 p43 p44 p45/sck p46/so p47/si n.c. 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 n.c. v ss p17 p16 p15 p14 p13 p12 p11 p10 mod0 n.c. (fpt-48p-m05) (top view) (top view) 65 v pp 66 a12 67 a7 68 a6 69 a5 70 a4 71 a3 72 a2 73 a1 74 a0 75 o1 76 o2 77 o3 78 v ss v cc 92 a14 91 a13 90 a8 89 a9 88 a11 87 oe 86 a10 85 ce 84 o8 83 o7 82 o6 81 o5 80 o4 79 1 p36/wto 2 p37/pto 3 p40 4 p41 5 p42 6 p43 7 p44/bz 8 p45/sck2 9 p46/so2 10 p47/si2 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p60/int0 23 p61/int1 24 p62/int2 25 p63/int3 26 p64 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p35/pwc 63 p34/ec 62 p33/si1 61 p32/so1 60 p31/sck1 59 p30/adst 58 v ss 57 p00/ad0 56 p01/ad1 55 p02/ad2 54 p03/ad3 53 p04/ad4 52 p05/ad5 51 p06/ad6 50 p07/ad7 49 p10/a08 48 p11/a09 47 p12/a10 46 p13/a11 45 p14/a12 44 p15/a13 43 p16/a14 42 p17/a15 41 p20/bufc 40 p21/hak 39 p22/hrq 38 p23/rdy 37 p24/clk 36 p25/wr 35 p26/rd 34 p27/ale 33 (mdp-64c-p02) each pin inside the dashed line is for mb89pv620 only.
MB89601r series 5 ? pin assignment on package top (mb89pv620 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67a1275a083o591a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p45/sck2 p46/so2 p47/si2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 p63/int3 p64 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/adst v ss p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 p44/bz p43 p42 p41 p40 p37/pto p36/wto v cc p35/pwc p34/ec p33/si1 p32/so1 p31/sck1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 84 83 82 81 80 79 78 94 95 96 65 66 67 68 (top view) (mqp-64c-p01) each pin inside the dashed line is for mb89pv620 only.
MB89601r series 6 n pin description ? MB89601r/603/p601 * : fpt-48p-m05 pin no. pin name circuit type function sqfp* 3 x0 a cystal oscillator pins 2x1 38 mod0 b operating mode selection pins connect directly to v ss . 35 mod1 14 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "l" is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 27 to 34 p00 to p07 d general-purpose i/o ports 39 to 46 p10 to p17 16 to 22 p30 to p36 e general-purpose i/o ports this port is a hysteresis input type. a software pull-up resistor is provided as an option. 23 p37/pto general-purpose i/o port this port is a hysteresis input type. also serves as the toggle output for the 8-bit pwm timer. a software pull-up resistor is provided as an option. 4 to 8 p40 to p44 g n-ch open-drain i/o port this port is a hysteresis input type. 9 p45/sck n-ch open-drain i/o port this port is a hysteresis input type. also serves as the clock i/o for the serial i/o. 10, 11 p46/so, p47/si n-ch open-drain i/o port this port is a hysteresis input type. also serves as the data output for the serial i/o. 15 p60/int i general-purpose input-only port also serves as an external interrupt input. this port is a hysteresis input type. 26 v cc power supply pin 47 v ss power supply (gnd) pin 1, 12, 13, 24, 25, 36, 37, 48 n.c. be sure to leave them open.
MB89601r series 7 ? mb89pv620 (continued) *1: mdp-64c-p02 *2: mqp-64c-p01 pin no. pin name circuit type function mdip *1 mqfp *2 30 23 x0 a crystal oscillator pins 31 24 x1 28 21 mod0 b operating mode selection pins connect directly to v cc or v ss . 29 22 mod1 27 20 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 56 to 49 49 to 42 p00/ad0 to p07/ad7 d general-purpose i/o ports when an external bus is used, this port function as multiplex pins of lower address output and data i/o. 48 to 41 41 to 34 p10/a08 to p17/a15 d general-purpose i/o ports when an external bus is used, this port function as a upper address output. 40 33 p20/bufc f general-purpose output-only port when an external bus is used, this port can also be used as a buffer control output by setting the bctr. 39 32 p21/hak f general-purpose output-only port when an external bus is used, this port can also be used as a hold-acknowledge by setting the bctr. 38 31 p22/hrq d general-purpose output-only port when an external bus is used, this port can also be used as a hold request input by setting the bctr. 37 30 p23/rdy d general-purpose output-only port when an external bus is used, this port functions as a ready input. 36 29 p24/clk f general-purpose output-only port when an external bus is used, this port functions as a clock output. 35 28 p25/wr f general-purpose output-only port when an external bus is used, this port functions as a write signal output. 34 27 p26/rd f general-purpose output-only port when an external bus is used, this port functions as a read signal output.
MB89601r series 8 (continued) (continued) *1: mdp-64c-p02 *2: mqp-64c-p01 pin no. pin name circuit type function mdip *1 mqfp *2 33 26 p27/ale f general-purpose output-only port when an external bus is used, this port functions as an address latch signal output. 58 51 p30/adst e general-purpose i/o port also serves as the external activation input for the a/d converter. this port is a hysteresis input type. 59 52 p31/sck1 e general-purpose i/o port also serves as the clock i/o for the serial i/o 1. this port is a hysteresis input type. 60 53 p32/so1 e general-purpose i/o port also serves as the data output for the serial i/o 1. this port is a hysteresis input type. 61 54 p33/si1 e general-purpose i/o port also serves as the data input for the serial i/o 1. this port is a hystereisis input type. 62 55 p34/ec e general-purpose i/o port also serves as the external clock input for the 16-bit timer/counter. this port is a hysteresis input type. 63 56 p35/pwc e general-purpose i/o port also serves as the measured-pulse input for the 8-bit pulse width-counter. this port is a hysteresis input type. 1 58 p36/wto e general-purpose i/o port also serves as the toggle output for the 8-bit pulse-width counter. this port is a hysteresis input type. 2 59 p37/pto e general-purpose i/o port also serves as the toggle output for the 8-bit pwm timer. this port is a hysteresis input type. 3 to 6 60 to 63 p40 to p43 g n-ch open-drain i/o ports this port is a hysteresis input type. 7 64 p44/bz g n-ch open-drain i/o port also serves as a buzzer output. this port is a hysteresis input type. 8 1 p45/sck2 g n-ch open-drain i/o port also serves as the clock i/o for the serial i/o 2. this port is a hysteresis input type. 9 2 p46/so2 g n-ch open-drain i/o port also serves as the data output for the serial i/o 2. this port is a hysteresis input type.
MB89601r series 9 (continued) *1: mdp-64c-p02 *2: mqp-64c-p01 pin no. pin name circuit type function mdip *1 mqfp *2 10 3 p47/si2 g n-ch open-drain i/o port also serves as the data i/o for the serial i/o 2. this port is a hysteresis input type. 11 to 18 4 to 11 p50/an0 to p57/an7 h n-ch open-drain output-only ports also serves as the analog input for the a/d converter. 22 to 25 15 to 18 p60/int0 to p63/int3 i general-purpose input-only ports also serves as an external interrupt input. this port is a hysteresis input type. 26 19 p64 i general-purpose input-only port this port is a hysteresis input type. 64 57 v cc power supply pin 32, 57 25, 50 v ss power supply (gnd) pins 19 12 av cc a/d converter power supply pin 20 13 avr a/d converter reference voltage input pin 21 14 av ss a/d converter power supply pin. use this port at the same voltage as v ss .
MB89601r series 10 ? external eprom pins (mb89pv620 only) pin no. pin name i/o function mdip mqfp 65 66 v pp o h level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 75 76 77 77 78 79 o1 o2 o3 i data input pins 78 80 v ss o power supply (gnd) pin 79 80 81 82 83 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins 84 87 ce o rom chip enable pin outputs h during standby. 85 88 a10 o address output pin 86 89 oe o rom output enable pin outputs l at all times. 87 88 89 91 92 93 a11 a9 a8 o address output pins 90 94 a13 o 91 95 a14 o 92 96 v cc o eprom power supply pin 65 76 81 90 n.c. internally connected pins be sure to leave them open.
MB89601r series 11 n i/o circuit type (continued) type circuit remarks a ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d?cmos i/o ? pull-up resistor optional (MB89601r/603 only) e ? cmos output ? hysteresis input ? software pull-up resistor optional x1 x0 standby control signal r p-ch n-ch p-ch r n-ch p-ch p-ch n-ch p-ch r
MB89601r series 12 (continued) type circuit remarks f ? cmos output g ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional (MB89601r/603 only) h ? n-ch open-drain output ? analog input ? pull-up resistor optional i ? hysteresis input ? pull-up resistor optional (MB89601r/603 only) n-ch p-ch n-ch p-ch r n-ch analog input p-ch p-ch r
MB89601r series 13 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than p40 to p47, p60 or if higher than the voltage which shows on section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 4. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 5. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
MB89601r series 14 n programming to the eprom on the mb89p601 the mb89p601 is an otprom version of the MB89601r series. 1. features ? 4-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 4-kbyte prom is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p601 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 32 kbytes (8000 h to ffff h ) the prom can be programmed as follows: ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 7000 h to 7fff h (note that addresses e000 h to ffff h while operating as a single chip assign to 7000 h to 7fff h in eprom mode). (3) program to 0000 h to 7fff h with the eprom programmer. 0000 h address i/o ram not available not available prom 4 kb 0080 h 0140 h 8000 h e000 h ffff h 0000 h 7000 h 7fff h eprom 4 kb vacancy (read value ff h ) eprom mode (corresponding addresses on the eprom programmer) single chip
MB89601r series 15 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: connect the adapter jumper pin to v ss when using. package compatible socket adapter fpt-48p-m05 rom-48qf-28dp-8l program, verify aging +150?, 48 hrs. data verification assembly
MB89601r series 16 n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv, mbm27c256a-20cz 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode, such as 32-kbyte prom, is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0006 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32(rectangle) rom-32lc-28dp-yg 0000 h address i/o ram not available prom 32 kb 0080 h 0480 h 8000 h ffff h 0000 h 7fff h eprom 32 kb corresponding addresses on the eprom programmer single chip
MB89601r series 17 n block diagram ram f 2 mc-8l cpu rom time-base timer external interrupt p60/int 8-bit serial i/o n-ch open-drain i/o port 8 p47/si p46/so p45/sck p44 p43 p42 p41 p40 internal bus x0 x1 oscillator rst clock controller reset circuit (wdt) 8-bit pwm timer 8 p37/pto p36 p35 p34 p33 p32 p31 p30 8 p17 p16 p15 p14 p13 p12 p11 p10 port 0 8 p07 p06 p05 p04 p03 p02 p01 p00 other pins v cc, v ss, mod0, mod1 port 1 port 3 port 6 cmos i/o port cmos i/o port cmos i/o port input port port 4
MB89601r series 18 n cpu core 1. memory space the microcontrollers of the MB89601r series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the MB89601r series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0480 h 8000 h ffff h mb89pv620 i/o ram 1 kb external area external rom 32 kb 0200 h register 0000 h 0080 h 0100 h f000 h ffff h mb89p601 MB89601r i/o ram 80 b not available rom 4 kb register 0140 h 00f0 h not available 0000 h 0080 h 0100 h e000 h ffff h mb89603 i/o ram 80 b not available rom 8 kb register 0140 h 00f0 h not available
MB89601r series 19 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
MB89601r series 20 the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
MB89601r series 21 the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to 32 banks can be used on the architecture, but only 8 banks can be used on the MB89601r series due to the restricted internal ram size. the bank currently in use is indicated by the register bank pointer (rp). note: for software development, take care that the usable register banks on the MB89601r/603 are different from that on the mb89pv620. on the mb89pv620, up to 32 banks can be used. register bank configuration r1 r2 r3 r4 r5 r6 r7 this address = 0100 h + 8 (rp) memory area 32 banks r0
MB89601r series 22 n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) spcr port 3 pull-up register 05 h vacancy 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc clock interrupt control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h vacancy 10 h vacancy 11 h (r) pdr6 port 6 data register 12 h (r/w) cntr pwm control register 13 h (w) comr pwm compare register 14 h vacancy 15 h vacancy 16 h vacancy 17 h vacancy 18 h vacancy 19 h vacancy 1a h vacancy 1b h vacancy 1c h vacancy 1d h vacancy 1e h (r/w) smr serial mode register 1f h (r/w) sdr serial data register
MB89601r series 23 (continued) note: do not use vacancies. address read/write register name register description 20 h vacancy 21 h vacancy 22 h vacancy 23 h vacancy 24 h (r/w) eic external interrupt control register 25 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
MB89601r series 24 n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v input voltage v i1 v ss C 0.3 v cc + 0.3 v except p40 to p47, p60 v i2 v ss C 0.3 v ss + 7.0 v p40 to p47, p60 output voltage v o1 v ss C 0.3 v cc + 0.3 v except p40 to p47 v o2 v ss C 0.3 v ss + 7.0 v p40 to p47 l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total average output current ? i olav ? 40 ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
MB89601r series 25 2. recommended operating conditions (v ss = 0.0 v) * : these values vary with the operating frequency. see figure 1. figure 1 operating voltage vs. clock operating frequency parameter symbol value unit remarks min. max. power supply voltage v cc 2.2* 6.0 v normal operation assurance range* MB89601r/603 2.7* 6.0 v normal operation assurance range* mb89p601 1.5 6.0 v retains the ram state in stop mode operating temperature t a C40 +85 c 1 2 3 4 5 6 1 operation assurance range operating voltage (v) 5 clock operating frequency (mhz) 234 6789 note: the shaded area is assured only for the MB89601r/603. 0
MB89601r series 26 3. dc characteristics (v cc = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17 ? 0.7 v cc ? v cc + 0.3 v v ihs1 p30 to p37, mod0, mod1, rst ? 0.8 v cc ? v cc + 0.3 v v ihs2 p40 to p47, p60 ? 0.8 v cc ? v ss + 6.0 v l level input voltage v il p00 to p07, p10 to p17 ? v ss - 0.3 ? 0.3 v cc v v ils p30 to p37, mod0, mod1, rst , p40 to p47, p60 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p40 to p47 v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p30 to p37 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol p00 to p07, p10 to p17, p30 to p37, p40 to p47 i ol = +1.8 ma ?? 0.4 v v ol2 rst i ol = +4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p60, mod0, mod1 0.0 v < v i < v cc ?? 5 m a without pull- up resistor pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p60, rst v i = 0.0 v 25 50 100 k w
MB89601r series 27 (continued) (v cc = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) * : the power supply current is measured at the external clock. note: a pull-up resistor for p00 to p07, p10 to p17, p40 to p47 and p60 is selectable on MB89601r/603 only. 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) note: t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. parameter symbol pin condition value unit remarks min. typ. max. power supply current* i cc v cc f c = 8 mhz normal operating mode 915ma f c = 8 mhz 10 18 ma mb89p601 i ccs f c = 8 mhz sleep mode 3 4 ma external clock i cch t a = +25 c stop mode 10 m a input capacitance c in other than v cc and v ss f = 1 mhz 10 pf parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t xcyl ns 0.2 v cc 0.2 v cc rst t zlzh
MB89601r series 28 (2) power-on reset (v ss = 0.0 v, t a = C40 c to +85 c) note: abrupt change in power supply voltage may cause a power-on reset. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. (3) clock timing (v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations parameter symbol pin condition value unit remarks min. max. clock frequency f c x0, x1 1 8 mhz clock cycle time t xycl x0, x1 125 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
MB89601r series 29 (4) instruction cycle (5) serial i/o timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s t inst = 0.5 m s when operating at f c = 8 mhz parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s 0.2 v cc 0.8 v cc x0 0.2 v cc t cr p wh p wl t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 t xcyl when a crystal or ceramic resonator is used when an external clock is used open x0 and x1 timing and conditions clock conditions
MB89601r series 30 0.8 v 2.4 v t scyc 2.4 v 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si t slsh 2.4 v 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si t shsl 0.8 v cc 0.2 v cc 0.2 v cc t slov t slov internal shift clock mode external shift clock mode
MB89601r series 31 (6) peripheral input timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 int 2 t inst * m s peripheral input l pulse width 1 t ihil1 2 t inst * m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc int 0.2 v cc t ilih1
MB89601r series 32 n example characteristics (1) l level output voltage (2) h level output voltage (3) h level input voltage/l level input voltage 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v v ol vs. i ol t a = +25 c i ol (ma) 0.6 v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v 0 0 1.0 v cc = 4.0 v i oh (ma) v cc ?v oh vs. i oh 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ? ? ? ? ? v cc ?v oh (v) v cc = 2.0 v t a = +25 c v cc = 2.5 v v cc = 3.0 v v cc = 5.0 v v cc = 6.0 v 123 456 7 v in (v) v in vs. v cc cmos input t a = +25? v cc (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 123 456 7 v in (v) v in vs. v cc cmos hysteresis input t a = +25? v cc (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v ils v ihs v ihs : threshold when input voltage in hysteresis characteristics is set to ??level v ils : threshold when input voltage in hysteresis characteristics is set to ??level
MB89601r series 33 (4) pull-up resistance r pull vs. v cc r pull (k w) 10 100 1000 500 50 1234 5 67v cc (v) t a = +25 c
MB89601r series 34 n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
MB89601r series 35 table 2 transfer instructions (48 instructions) note during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
MB89601r series 36 table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
MB89601r series 37 (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
MB89601r series 38 n instruction map h l 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
MB89601r series 39 n mask options *1: a pull-up resistor for p30 to p37 is not set when ordering masking. it is set by software. *2: when a pull-up resistor for p40 to p47 and p60 is selected, the input signal exceeding v cc voltage is not possible. n ordering information no. part number MB89601r mb89603 mb89p601 mb89pv620 specifying procedure specify when ordering masking setting not possible setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p40 to p47 *2 , p60 *2 selectable by pin fixed to without pull- up resistor fixed to without pull-up resistor p30 to p33 *1 selectable by pin (software pull-up resistor) can be set per pin (software pull-up resistor) p33 to p37 *1 selectable by 4 pins (software pull-up resistor) can be set per 4 pins (software pull-up resistor) 2 power-on reset selection with power-on reset without power-on reset selectable fixed to with power-on reset fixed to with power-on reset 3 selection of the oscillation stabilization time crystal oscillator: (2 18 /f c ) ceramic oscillator: (2 12 /f c ) selectable fixed to crystal oscillator (2 18 /f c ) fixed to crystal oscillator (2 18 /f c ) 4 reset pin output with reset output without reset output selectable fixed to with reset output fixed to with reset output part number package remarks MB89601rpfv mb89603pfv mb89p601pfv 48-pin plastic sqfp (fpt-48p-m05) mb89pv620c-sh 64-pin ceramic mdip (mdp-64c-p02) mb89pv620cf 64-pin ceramic mqfp (mqp-64c-p01)
MB89601r series 40 n package dimensions 48 pin, plastic lqfp (fpt-48p-m05) dimensions in mm (inches). 64-pin ceramic mdip (mdp-64c-p02) dimensions in mm (inches). +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 +0.08 C0.03 +.003 C.001 (stand off) lead no. index 36 37 48 112 13 24 25 0 10 details of "a" part (.004.004) 0.100.10 (.020.008) 0.500.20 "a" 7.000.10(.276.004)sq 1.50 .059 0.127 .005 0.18 .007 nom (.315) 8.00 ref (.217) 5.50 9.000.20(.354.008)sq (.0197.0031) 0.500.08 0.10(.004) 1994 fujitsu limited f48013s-2c-4 c +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc-1-4 c
MB89601r series 41 64-pin ceramic mqfp (mqp-64c-p01) dimensions in mm (inches). +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c
MB89601r series 42 memo
MB89601r series 43 memo
MB89601r series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 9703 ? fujitsu limited printed in japan

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